1. Field of the Invention
Generally, the present invention relates to the formation of integrated circuits, and, more particularly, to the formation of field effect transistors of different conductivity having a channel region with a different specified intrinsic strain to improve the charge carrier mobility in each of the different transistor types.
2. Description of the Related Art
The fabrication of integrated circuits requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips and the like, CMOS technology is currently the most promising approach, due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of complementary transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with a lightly doped channel region disposed between the drain region and the source region.
The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, substantially depends on the dopant concentration, the mobility of the charge carriers, and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially influences the performance of the MOS transistors. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, renders the channel length a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. One major problem in this respect is the development of enhanced photolithography and etch strategies to reliably and reproducibly create circuit elements of critical dimensions, such as the gate electrode of the transistors, for a new device generation. Moreover, highly sophisticated dopant profiles, in the vertical direction as well as in the lateral direction, are required in the drain and source regions to provide low sheet and contact resistivity in combination with a desired channel controllability. In addition, the vertical location of the PN junctions with respect to the gate insulation layer also represents a critical design criterion in view of leakage current control, since reducing the channel length also requires reducing the depth of the drain and source regions with respect to the interface formed by the gate insulation layer and the channel region, thereby requiring sophisticated implantation techniques. According to other approaches, epitaxially grown regions are formed with a specified offset to the gate electrode, which are referred to as raised drain and source regions, to provide increased conductivity of the raised drain and source regions, while at the same time maintaining a shallow PN junction with respect to the gate insulation layer.
Since the continuous size reduction of the critical dimensions, i.e., the gate length of the transistors, necessitates great efforts for the adaptation and possibly the new development of process techniques concerning the above-identified process steps, it has been proposed to also enhance device performance of the transistor elements by increasing the charge carrier mobility in the channel region for a given channel length. In principle, at least two mechanisms may be used, in combination or separately, to increase the mobility of the charge carriers in the channel region. First, the dopant concentration within the channel region may be reduced, thereby reducing scattering events for the charge carriers and thus increasing the conductivity. However, reducing the dopant concentration in the channel region significantly affects the threshold voltage of the transistor device, thereby making a reduction of the dopant concentration a less attractive approach, unless other mechanisms are developed to adjust a desired threshold voltage. Second, the lattice structure in the channel region may be modified, for instance by creating tensile or compressive strain, which results in a modified mobility for electrons and holes, respectively. For example, creating tensile strain in the channel region increases the mobility of electrons, wherein, depending on the magnitude of the tensile strain, an increase in mobility of up to 120% may be obtained, which, in turn, may directly translate into a corresponding increase in the conductivity. On the other hand, compressive strain in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors. Therefore, in some conventional approaches, for instance, a silicon/germanium layer or a silicon/carbon layer is provided in or below the channel region to create tensile or compressive strain therein. Although the transistor performance may be considerably enhanced by the introduction of strain-creating layers in or below the channel region, significant efforts have to be made to implement the formation of corresponding layers into the conventional and well-approved CMOS technique. For instance, additional epitaxial growth techniques have to be developed and implemented into the process flow to form the germanium- or carbon-containing stress layers at appropriate locations in or below the channel region. Hence, process complexity is significantly increased, thereby also increasing production costs and the potential for a reduction in production yield.
In other approaches, stress from a contact etch stop layer that is required on top of the transistors to control a contact etch process is used to induce strain in the channel regions of the transistors, wherein compressive strain is created in the P-channel transistor, while tensile strain is created in the N-channel transistor.
For this purpose, sidewall spacers may be removed prior to the formation of the contact etch stop layers in order to more closely position the layers to the channel regions and to enhance stress transfer controllability by substantially reducing the effect of the sidewall spacers on the finally achieved strain. However, this conventional approach, although offering substantial performance advantages, may bring about some drawbacks that may partially offset the benefits accomplished by the enhanced strain engineering, as will be described with reference to FIG. 1a-1d. 
FIG. 1a schematically shows a cross-sectional view of a semiconductor device 150 comprising an NMOS transistor element 100N and a PMOS transistor element 100P. The transistor elements 100N, 100P may be provided in the form of silicon-on-insulator (SOI) devices. Thus, the semiconductor device 150 comprises a silicon substrate 101 having formed thereon an insulating layer 102, such as a buried silicon dioxide layer, followed by a crystalline silicon layer 103. The transistors 100N, 100P may be separated from each other by an isolation structure 120, for instance in the form of a shallow trench isolation. The transistor 100N further comprises a gate electrode structure 105 comprising a polysilicon portion 106. The gate electrode structure 105 further comprises a gate insulation layer 107 separating the gate electrode structure 105 from a channel region 104, which, in turn, laterally separates appropriately doped source and drain regions 111 connected to extensions regions 114. A spacer element 110 is formed adjacent to the sidewalls of the gate electrode structure 105 and is separated therefrom by a liner 109, which is also formed between the source and drain regions 111 and the spacer element 110.
The second transistor 100P may have substantially the same configuration and the same components, wherein the channel region 104 and the drain and source regions 111 include different dopants compared to the respective regions of the transistor 100N.
A typical process flow for forming the semiconductor device 150 as shown in FIG. 1a may comprise the following processes. The substrate 101, the insulating layer 102 and the silicon layer 103 may be formed by advanced wafer bond techniques when the semiconductor device 150 is to represent an SOI device, or the substrate 101 may be provided without the insulating layer 102, as a bulk semiconductor substrate, wherein the silicon layer 103 may represent an upper portion of the substrate, or may be formed by epitaxial growth techniques. Thereafter, the gate insulation layer 107 may be deposited and/or formed by oxidation in accordance with well-established process techniques, followed by the deposition of polysilicon, by means of low pressure chemical vapor deposition (LPCVD). Thereafter, the polysilicon and the gate insulation layer 107 may be patterned by sophisticated photolithography and etch techniques in accordance with well-established process recipes. Next, implantation cycles, in combination with the manufacturing process for forming the spacer element 110, may be performed, wherein the spacer element 110 may be formed as two or more different spacer elements with intermediate implantation processes when a sophisticated laterally profiled dopant concentration is required for the drain and source regions 111. For example, the extension regions 114 of reduced penetration depth may be required. Next, any anneal cycles for activating and partially curing implantation-induced crystal damage may follow.
Thereafter, the spacer elements 110 may be removed by well-established highly selective etch recipes, wherein the etch chemistry is selected so as to be selective with respect to polysilicon and silicon dioxide, so that the spacer 110, comprised of silicon nitride, may be efficiently removed substantially without significant material erosion in the polysilicon portion 106 and the drain and source regions 111. Next, metal silicide regions may be formed in the polysilicon portion 106 and the drain and source regions 111 by depositing a refractory metal, such as cobalt, nickel and the like, and performing an appropriate anneal sequence for initiating a chemical reaction between the silicon and the refractory metal.
FIG. 1b schematically shows the semiconductor device 150 after the completion of the above-described process sequence. Hence, the device 150 comprises metal silicide regions 112 in and on the drain and source regions 111 and a corresponding metal silicide region 108 in the gate electrodes 105. Thereafter, a dielectric layer stack is formed for providing a first contact etch stop layer having a specified intrinsic stress.
FIG. 1c schematically shows the semiconductor device 150 with a first contact etch stop layer 116 formed on a first etch stop layer 118 and a second etch stop layer 117 formed above the first contact etch stop layer 116. Typically, the transistor elements 100N, 100P are embedded in an interlayer dielectric material (not shown in FIG. 1c), over which corresponding metallization layers are to be formed to establish the required electrical connections between the individual circuit elements. The interlayer dielectric material has to be patterned to provide contact to the gate electrode structure 105 and the drain and source regions 111 by means of an anisotropic etch process. Since this anisotropic etch process has to be performed to different depths, a reliable etch stop layer, that is, the contact etch stop layer 116, in addition to a second etch stop layer still to be formed, is provided to reliably control the etch process. Frequently, the interlayer dielectric material is comprised of silicon dioxide and thus the contact etch stop layer 116 may comprise silicon nitride, as silicon nitride exhibits a good etch selectivity for well-established anisotropic recipes for etching silicon dioxide. Moreover, silicon nitride may be deposited in accordance with well-established deposition recipes, wherein the deposition parameters may be appropriately adjusted for providing a specified intrinsic mechanical stress while nevertheless maintaining the desired high etch selectivity to silicon dioxide. Typically, silicon nitride is deposited by plasma enhanced chemical vapor deposition (PECVD) wherein, for example, parameters of the plasma atmosphere, such as bias power supplied to the plasma atmosphere, may be varied in order to adjust the mechanical stress created in the silicon nitride layer as deposited. Thus, the stress in the first contact etch stop layer 116 may be determined by the deposition conditions, wherein, for instance, a compressive stress in silicon nitride up to approximately 1.5 GPa and also a tensile stress up to approximately 1.5 GPa may be achieved by appropriately selecting deposition parameters.
The first etch stop layer 118 and the second etch stop layer 117 may exhibit a significantly reduced thickness compared to the contact etch stop layer 116, since especially the first etch stop layer 118 may act, in principle, as an unwanted “buffer” layer, which may reduce, to a certain degree, the mechanical stress transferred from the respective contact etch stop layer into the channel regions 104. The layers 118 and 117 may be provided in the form of silicon dioxide.
FIG. 1d schematically shows the semiconductor device 150 with a resist mask 140 that exposes the first transistor element 100N and the layer portions formed thereon, while covering the second transistor 100P and the layer portions formed thereon. Based on the resist mask 140, the exposed second etch stop layer 117 may be removed on the basis of an isotropic etch process, thereby leaving residues 117R (see FIG. 1e) at sidewall portions of the layer 116. Subsequently, the resist mask 140 may be removed or may be maintained during a further etch process for removing the first contact etch stop layer 116 formed above the first transistor 100N.
FIG. 1e schematically shows the device 150, with the resist mask 140 and the etch stop layer 117 above the first transistor 100N removed, except for the residues 117R. Moreover, the device 150 is subjected to an etch process 160 for removing substantial portions of the first contact etch stop layer 116 above the first transistor element 100N, wherein the remaining second etch stop layer 117 above the transistor 100P may act as an etch mask, while the residues 117R may negatively affect the removal process in the transistor 100N.
FIG. 1f schematically shows the device 150 after the completion of the above-described etch process 160. Due to the residues 117R during the etch process 160, residuals of the first contact etch stop layer 116, referred to as 116R, may be left on sidewalls of the gate structure 105, thereby significantly affecting the stress transfer mechanism in the first transistor 100N after a second contact etch stop layer (not shown) is deposited with a corresponding intrinsic stress, as is required for performance enhancement of the first transistor element 100N. For example, if the first contact etch stop layer 116 is provided with compressive stress so as to enhance performance of the transistor 100P, the mechanism for transferring tensile stress into the channel region of the first transistor 100N by forming an appropriate second contact etch stop layer is at least partially compensated for by the residual “spacers” 116R having the compressive stress. A further “over-etching” during the etch process 160 may, however, be less desirable so as to not unduly deteriorate the etch stop layer 118, thereby otherwise risking a high degree of metal silicide degradation, which may then negatively impact the further device processing, as well as the electrical performance thereof.
In view of the situation described above, there exists a need for an improved technique that enables an efficient stress transfer mechanism while avoiding or at least reducing the effects of one or more of the problems identified above.